The present invention relates generally to an interrupt redirection apparatus and method for inter-processor communication (IPC), and more particularly to an apparatus and method, in which a master processor redirects an interrupt to a slave processor in a system-on-chip (SoC) having two or more ARM processor cores.
Generally, in order to construct a multiprocessor system using a plurality of processors, interrupt distribution and inter-processor communication must be supported.
Interrupts are used to inform processors of the occurrence of irregular and exceptional events, and are classified into internal interrupts and external interrupts. Such an internal interrupt is an event occurring in hardware within the processor while the process executes instructions, and occurs in cases such as the execution of a privileged instruction and the generation of overflow of an arithmetic logic unit. Such an external interrupt (hereinafter, referred to as an interrupt) is used for informing processors of the generation of errors of hardware outside the processor, like a peripheral device, and the operation state of peripheral hardware.
The above description of the typical interrupt is disclosed in detail in xe2x80x9cComputer System Architecturexe2x80x9d by xe2x80x9cM. M. Manoxe2x80x9d and xe2x80x9cComputer Architecture and Organizationxe2x80x9d by xe2x80x9cJohn P. Hayesxe2x80x9d.
A conventional method for informing a processor of an interrupt is to apply an interrupt signal to the processor. Interrupt signals differ from one processor to another, and, for example, for an ARM processor, two interrupt signals composed of a Fast Interrupt Request (FIQ) and an Interrupt ReQuest (IRQ) are provided.
Because the interrupt can be generated in a variety of peripheral devices outside the processor, an interrupt controller is used for collecting interrupt signals received from a plurality of interrupt sources and sending the interrupt signals to the processor as interrupt request signals.
In a multiprocessor system using a plurality of processors, inter-processor communication is required. In the multiprocessor system, the processors divide a specific task and process the divided operations simultaneously. At this time, inter-processor communication is required for performing the synchronization between processors and informing the processors of status thereof. Here, a common variable method that sets the threshold region in a shared memory and constructs a common variable in the threshold region, and a message passing method that constructs a specific communication channel between processors, and transmits/receives messages through the communication channel are used in the inter-processor communication.
The communication method using the common variable is used in the multiprocessor system employing the shared memory and can be realized using only software without additional hardware devices. On the other hand, the message passing method uses a communication channel provided by hardware regardless of the sharing of the memory.
The above description of the conventional inter-processor communication is disclosed in detail in xe2x80x9cAdvanced Computer Architecture, Parallelism, Scalability, Programmabilityxe2x80x9d by xe2x80x9cKai Whangxe2x80x9d.
The ARM (Advanced RISC Machines) processor does not provide a multiprocessor function, for example, interrupt redistribution and communication channel hardware according to its structural characteristics. Further, in a xe2x80x9cPrimeCellxe2x80x9d, which is a semiconductor library provided by ARM Corporation, design resources for supporting the multiprocessor are not supported.
Meanwhile, conventional technologies related to the interrupt distribution and the inter-processor communication are described as follows.
The ARM Corporation provides an interrupt controller named a Vectored Interrupt Controller (VIC) which performs a vectored interrupt control function so as to design an ARM processor based system-on-chip. The vectored interrupt controller collects interrupts generated in a plurality of peripheral devices and transfers the interrupts to the IRQ and FIQ which are interrupt reception signals of the ARM processor using a point-to-point connection method. The vectored interrupt controller is an interrupt controller for a single ARM processor, and is disadvantageous in that, when it is adapted to a design structure having a plurality of ARM processors therein, each exclusive vectored interrupt controller must be connected to each ARM processor. Further, the vectored interrupt controller is problematic in that, because the same interrupt source is connected to a plurality of vectored interrupt controllers, it is not clear which processor must process a generated interrupt, thus causing a problem in software development. In a design structure using a plurality of ARM processors, the inter-processor communication must be supported, and in the inter-processor communication, the message passing method for asynchronously transferring messages to the processor as well as the communication using a predetermined region of the shared memory must be supported. In order to perform an asynchronous inter-processor communication, a function for requesting an interrupt between processors is required. However, the vectored interrupt controller provided by the ARM Corporation is problematic in that it must employ a plurality of vectored interrupt controllers so as to allow mutual communication between the processors.
Further, U.S. Pat. No. 6,189,065 B1 owned by IBM Corporation discloses the invention entitled xe2x80x9cMethod and Apparatus for interrupt load balancing for PowerPC processorsxe2x80x9d, as described below in detail.
In the above patent, interrupt buses between processors are constructed in the form of a xe2x80x9cDaisy-chainxe2x80x9d using interrupt reception and transmission hardware devices included in a processor. Further, an interrupt queue and a counter are included in the processor. The above patent primarily claims hardware having a function such that if an interrupt is transferred to a specific processor, the hardware confirms the interrupt counter in the processor and transmits the interrupt to an interrupt reception unit of the processor adjacent to the specific processor with the xe2x80x9cDaisy-chainxe2x80x9d construction if the counted value exceeds a predetermined number, and an interrupt load distribution method utilizing the hardware. However, the invention of the patent is disadvantageous in that the interrupt transmission and reception hardware devices are additionally constructed inside or outside each processor, interrupt transmission and reception units between adjacent processors are connected to each other with the xe2x80x9cDaisy-Chainxe2x80x9d construction, and especially, an additional interrupt bus must be constructed so as to transmit/receive an interrupt between processors. Consequently, the invention cannot be applied to design structures using ARM processors.
Further, U.S. Pat. No. 6,237,058 B1 owned by NEC Corporation discloses the invention entitled xe2x80x9cInterrupt load distribution system for shared bus type multiprocessor systems and interrupt load distribution methodxe2x80x9d, as described below in detail.
Referring to the patent, in common bus based multiprocessor systems, the operating system (OS) stores interrupt processing load details according to processors through a table managing interrupt processing statistics according to processors. The operating system constructs an interrupt scheduling information table therein on the basis of the interrupt statistics table according to processors. The interrupt scheduling information table is used as a table for determining which processor processes a corresponding interrupt according to kinds of interrupts.
In order to perform an interrupt scheduling operation, an input/output controller has an interrupt target information table for designating target processors according to interrupts therein, and the operating system periodically updates the interrupt target information table to uniformly distribute interrupts to each processor.
The above patent primarily claims a method for adding a function for managing interrupt processing details to the operating system, controlling the interrupt target information table included in the input/output controller on the basis of the function, and then enabling the uniform distribution of the interrupt loads in the common bus based multiprocessing system. However, the invention of the patent is disadvantageous in that it requires the support of the operating system for interrupt processing statistics and the input/output controller must have the interrupt target information table therein.
In U.S. Pat. No. 6,154,785 entitled xe2x80x9cInter-processor Communication Systemxe2x80x9d and owned by Network Equipment Technology Corporation, an inter-processor communication method in a multiprocessor system is disclosed, as described below in detail.
In the patent, processors use exclusive controllers for the inter-processor communication, and these exclusive controllers are connected to each other through an inter-processor communication bus. The exclusive controllers are each comprised of a communication command register, a semaphore register, a status register, a local memory interface unit, and an inter-processor communication bus interface unit. Each processor generates a communication request by writing a communication command into the command register of the exclusive controller, and the exclusive controller decodes the command in the command register and transmits the communication contents to an opposite exclusive controller through the inter-processor communication bus. Each processor recognizes the results of message transmission or reception by polling the status register of the exclusive controller or receiving an interrupt. The inter-processor communication method is preferably designed to transmit and receive short messages between master and slave processors, as in the case of communicating between a management processor and each node processor in a network equipment construction, or a case of transmitting and receiving management messages between a host processor and a network processor in a network interface device.
The above patent relates to an inter-processor communication apparatus and method constructed using exclusive controllers proposed for inter-processor communication and an inter-processor communication bus used for providing the connection between the exclusive controllers. Further, the patent primarily claims the construction of the exclusive controller, a message format, and a message transmission/reception method. However, the invention of the patent is problematic in that it must have each exclusive controller according to processors, and it utilizes the inter-processor communication exclusive bus for connecting between exclusive controllers.
Accordingly, the present invention has been made keeping in mind the above problems occurring in the prior art, and an object of the present invention is to provide an interrupt redirection apparatus and method for inter-processor communication, in which a master processor redirects a received interrupt to a slave processor and which generates an interrupt for supporting inter-processor communication when a system-on-chip having a plurality of ARM processors therein is designed.
In order to accomplish the above object, the present invention provides an interrupt redirection apparatus for a system-on-chip having a plurality of ARM processors and a vectored interrupt controller for receiving interrupts generated peripheral hardware, and transferring each interrupt to an ARM processor designated as a master processor. The interrupt redirection apparatus comprises an interrupt command register for designating targets and kinds of each interrupt to perform a function for receiving an interrupt redirection command through a bus interface unit and activating an interrupt request signal connected to a slave processor such that the master processor resends a received corresponding interrupt to an ARM processor designated as the slave processor; an interrupt data register for designating the contents of each interrupt; an interrupt signal generation unit for reading the contents in the interrupt command register and activating an interrupt request signal connected to a specific ARM processor; and a bus interface unit used for providing read and write accesses of both the interrupt command register and the interrupt data register.